The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting semiconductor device structures including a novel design for a uniform bottom spacer of a vertical transport field effect transistor.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as field effect transistors (FETs), are fabricated on a single wafer. Some non-planar transistor device architectures, such as vertical field effect transistors (VFETs), employ semiconductor fins channels and side-gates that can be contacted outside the active region, resulting in increased device density and performance over lateral devices. VFETs are one of the promising alternatives to standard lateral FET structures due to benefits, among others, in terms of reduced circuit footprint. In this type of structure, the current flow is perpendicular to a supporting wafer, unlike the lateral current flow in fin-type FETs (FinFETs). When forming VFETs, spacers need to be provided between and around the vertical fin channel to isolate the bottom source or drain (S/D) region and the top S/D region.